// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "mt7981.dtsi"

/ {
	model = "OpenEmbed SOM7981";
	compatible = "openembed,som7981", "mediatek,mt7981";

	aliases {
		led-boot = &wlan2g_led;
		led-failsafe = &wlan2g_led;
		led-upgrade = &wlan2g_led;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		reg = <0 0x40000000 0 0x40000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
		};

		button-wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		led-0 {
			function = LED_FUNCTION_LAN;
			color = <LED_COLOR_ID_AMBER>;
			gpios = <&pio 8 GPIO_ACTIVE_LOW>;
		};

		led-1 {
			function = LED_FUNCTION_LAN;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&pio 13 GPIO_ACTIVE_LOW>;
		};

		wlan2g_led: led-2 {
			function = LED_FUNCTION_WLAN_2GHZ;
			color = <LED_COLOR_ID_RED>;
			gpios = <&pio 34 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "phy0tpt";
		};

		led-3 {
			function = LED_FUNCTION_WLAN_5GHZ;
			color = <LED_COLOR_ID_RED>;
			gpios = <&pio 35 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "phy1tpt";
		};
	};
};

&eth {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";
		phy-handle = <&phy0>;
		nvmem-cells = <&macaddr_factory_a 0>;
		nvmem-cell-names = "mac-address";
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "gmii";
		phy-handle = <&int_gbe_phy>;
		nvmem-cells = <&macaddr_factory_a 1>;
		nvmem-cell-names = "mac-address";
	};
};

&mdio_bus {
	phy0: ethernet-phy@5 {
		reg = <5>;
		compatible = "ethernet-phy-ieee802.3-c45";
		phy-mode = "2500base-x";
		reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
		reset-assert-us = <10000>;
		reset-deassert-us = <50000>;
		realtek,aldps-enable;
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	status = "okay";

	spi_nand: flash@0 {
		compatible = "spi-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;

		spi-max-frequency = <52000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bl2";
				reg = <0x000000 0x100000>;
				read-only;
			};

			partition@100000 {
				label = "u-boot-env";
				reg = <0x100000 0x80000>;
			};

			partition@180000 {
				compatible = "nvmem-cells";
				label = "factory";
				reg = <0x180000 0x100000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					eeprom_factory_0: eeprom@0 {
						reg = <0x0 0x1000>;
					};

					macaddr_factory_a: macaddr@a {
						compatible = "mac-base";
						reg = <0xa 0x6>;
						#nvmem-cell-cells = <1>;
					};
				};
			};

			partition@280000 {
				label = "config";
				reg = <0x280000 0x100000>;
				read-only;
			};

			partition@380000 {
				label = "fip";
				reg = <0x380000 0x200000>;
				read-only;
			};

			partition@580000 {
				label = "ubi";
				reg = <0x580000 0xf880000>;
			};
		};
	};
};

&pio {
	spi0_flash_pins: spi0-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};

		conf-pu {
			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
			drive-strength = <8>;
			mediatek,pull-up-adv = <0>;
		};

		conf-pd {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
			drive-strength = <8>;
			mediatek,pull-down-adv = <0>;
		};
	};
};

&uart0 {
	status = "okay";
};

&usb_phy {
	status = "okay";
};

&watchdog {
	status = "okay";
};

&wifi {
	nvmem-cells = <&eeprom_factory_0>;
	nvmem-cell-names = "eeprom";
	status = "okay";
};

&xhci {
	status = "okay";
};
