// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include <dt-bindings/clock/rtl83xx-clk.h>

/dts-v1/;

#define STRINGIZE(s) #s
#define LAN_LABEL(p, s) STRINGIZE(p ## s)
#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)

#define INTERNAL_PHY(n) \
	phy##n: ethernet-phy@##n { \
		reg = <##n>; \
		compatible = "ethernet-phy-ieee802.3-c22"; \
		phy-is-integrated; \
	};

#define EXTERNAL_PHY(n) \
	phy##n: ethernet-phy@##n { \
		reg = <##n>; \
		compatible = "ethernet-phy-ieee802.3-c22"; \
	};

#define EXTERNAL_SFP_PHY(n) \
	phy##n: ethernet-phy@##n { \
		compatible = "ethernet-phy-ieee802.3-c22"; \
		sfp; \
		media = "fibre"; \
		reg = <##n>; \
	};

#define EXTERNAL_SFP_PHY_FULL(n, s) \
	phy##n: ethernet-phy@##n { \
		compatible = "ethernet-phy-ieee802.3-c22"; \
		sfp = <&sfp##s>; \
		reg = <##n>; \
	};

#define SWITCH_PORT(n, s, m) \
	port##n: port@##n { \
		reg = <##n>; \
		label = SWITCH_PORT_LABEL(s) ; \
		phy-handle = <&phy##n>; \
		phy-mode = #m ; \
	};

#define SWITCH_SFP_PORT(n, s, m) \
	port##n: port@##n { \
		reg = <##n>; \
		label = SWITCH_PORT_LABEL(s) ; \
		phy-handle = <&phy##n>; \
		phy-mode = #m ; \
		fixed-link { \
			speed = <1000>; \
			full-duplex; \
		}; \
	};

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "realtek,rtl838x-soc";

	osc: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	ccu: clock-controller {
		compatible = "realtek,rtl8380-clock";
		#clock-cells = <1>;
		clocks = <&osc>;
		clock-names = "ref_clk";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "mips,mips4KEc";
			reg = <0>;
			clocks = <&ccu CLK_CPU>;
			operating-points-v2 = <&cpu_opp_table>;
		};
	};

	cpu_opp_table: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <325000000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <350000000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <375000000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <400000000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <425000000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <450000000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <475000000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <500000000>;
		};
	};

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	cpuintc: cpuintc {
		compatible = "mti,cpu-interrupt-controller";
		#address-cells = <0>;
		#interrupt-cells = <1>;
		interrupt-controller;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x18000000 0x10000>;

		intc: interrupt-controller@3000 {
			compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
			reg = <0x3000 0x18>;
			interrupt-controller;
			#interrupt-cells = <2>;

			interrupt-parent = <&cpuintc>;
			interrupts = <2>, <3>, <4>, <5>, <6>;
		};

		spi0: spi@1200 {
			compatible = "realtek,rtl8380-spi";
			reg = <0x1200 0x100>;

			#address-cells = <1>;
			#size-cells = <0>;
		};

		timer0: timer@3100 {
			compatible = "realtek,rtl8380-timer", "realtek,otto-timer";
			reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
			      <0x3130 0x10>, <0x3140 0x10>;

			interrupt-parent = <&intc>;
			interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
			clocks = <&ccu CLK_LXB>;
		};

		uart0: uart@2000 {
			compatible = "ns16550a";
			reg = <0x2000 0x100>;

			clocks = <&ccu CLK_LXB>;

			interrupt-parent = <&intc>;
			interrupts = <31 1>;

			reg-io-width = <1>;
			reg-shift = <2>;
			fifo-size = <1>;
			no-loopback-test;
		};

		uart1: uart@2100 {
			pinctrl-names = "default";
			pinctrl-0 = <&enable_uart1>;

			compatible = "ns16550a";
			reg = <0x2100 0x100>;

			clocks = <&ccu CLK_LXB>;

			interrupt-parent = <&intc>;
			interrupts = <30 0>;

			reg-io-width = <1>;
			reg-shift = <2>;
			fifo-size = <1>;
			no-loopback-test;

			status = "disabled";
		};

		watchdog0: watchdog@3150 {
			compatible = "realtek,rtl8380-wdt";
			reg = <0x3150 0xc>;

			realtek,reset-mode = "soc";

			clocks = <&ccu CLK_LXB>;
			timeout-sec = <30>;

			interrupt-parent = <&intc>;
			interrupt-names = "phase1", "phase2";
			interrupts = <19 3>, <18 4>;
		};

		gpio0: gpio-controller@3500 {
			compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
			reg = <0x3500 0x20>;

			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <24>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupts = <23 3>;
		};
	};

	pinmux: pinmux@1b001000 {
		compatible = "pinctrl-single";
		reg = <0x1b001000 0x4>;

		pinctrl-single,bit-per-mux;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x1>;
		#pinctrl-cells = <2>;

		enable_uart1: pinmux_enable_uart1 {
			pinctrl-single,bits = <0x0 0x10 0x10>;
		};
	};

	/* LED_GLB_CTRL */
	pinmux_led: pinmux@1b00a000 {
		compatible = "pinctrl-single";
		reg = <0x1b00a000 0x4>;

		pinctrl-single,bit-per-mux;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x1>;
		#pinctrl-cells = <2>;

		/* enable GPIO 0 */
		pinmux_disable_sys_led: disable_sys_led {
			pinctrl-single,bits = <0x0 0x0 0x8000>;
		};
	};

	ethernet0: ethernet@1b00a300 {
		compatible = "realtek,rtl838x-eth";
		reg = <0x1b00a300 0x100>;
		interrupt-parent = <&intc>;
		interrupts = <24 3>;
		#interrupt-cells = <1>;
		phy-mode = "internal";

		fixed-link {
			speed = <1000>;
			full-duplex;
		};
	};

	sram0: sram@9f000000 {
		compatible = "mmio-sram";
		reg = <0x9f000000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x9f000000 0x10000>;
	};

	switch0: switch@1b000000 {
		compatible = "realtek,rtl83xx-switch";

		interrupt-parent = <&intc>;
		interrupts = <20 2>;
	};
};
