From 24025a2dcf1248079dd3019fac6ed955252d277f Mon Sep 17 00:00:00 2001
From: Imre Kaloz <kaloz@openwrt.org>
Date: Mon, 14 Jul 2008 21:56:34 +0200
Subject: [PATCH] Add support for the Compex WP18 / NP18A boards

Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
---

--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -85,6 +85,14 @@ config MACH_SIDEWINDER
 	  Engineering Sidewinder board. For more information on this
 	  platform, see http://www.adiengineering.com
 
+config MACH_COMPEXWP18
+	bool "Compex WP18 / NP18A"
+	select PCI
+	help
+	  Say 'Y' here if you want your kernel to support Compex' 
+	  WP18 or NP18A boards. For more information on this
+	  platform, see http://www.compex.com.sg/home/OEM/product_ap.htm
+
 config ARCH_IXDP425
 	bool "IXDP425"
 	help
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -21,6 +21,7 @@ obj-pci-$(CONFIG_MACH_FSG)		+= fsg-pci.o
 obj-pci-$(CONFIG_MACH_ARCOM_VULCAN)	+= vulcan-pci.o
 obj-pci-$(CONFIG_MACH_PRONGHORN)	+= pronghorn-pci.o
 obj-pci-$(CONFIG_MACH_SIDEWINDER)	+= sidewinder-pci.o
+obj-pci-$(CONFIG_MACH_COMPEXWP18)	+= ixdp425-pci.o
 
 obj-y	+= common.o
 
@@ -43,6 +44,7 @@ obj-$(CONFIG_MACH_GORAMO_MLR)	+= goramo_
 obj-$(CONFIG_MACH_ARCOM_VULCAN)	+= vulcan-setup.o
 obj-$(CONFIG_MACH_PRONGHORN)	+= pronghorn-setup.o
 obj-$(CONFIG_MACH_SIDEWINDER)	+= sidewinder-setup.o
+obj-$(CONFIG_MACH_COMPEXWP18)	+= compex42x-setup.o
 
 obj-$(CONFIG_PCI)		+= $(obj-pci-$(CONFIG_PCI)) common-pci.o
 obj-$(CONFIG_IXP4XX_QMGR)	+= ixp4xx_qmgr.o
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/compex42x-setup.c
@@ -0,0 +1,141 @@
+/*
+ * arch/arm/mach-ixp4xx/compex-setup.c
+ *
+ * Compex WP18 / NP18A board-setup
+ *
+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
+ *
+ * based on coyote-setup.c:
+ *	Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <Kaloz@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data compex42x_flash_data = {
+	.map_name	= "cfi_probe",
+	.width		= 2,
+};
+
+static struct resource compex42x_flash_resource = {
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device compex42x_flash = {
+	.name		= "IXP4XX-Flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data = &compex42x_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &compex42x_flash_resource,
+};
+
+static struct resource compex42x_uart_resources[] = {
+	{
+		.start		= IXP4XX_UART1_BASE_PHYS,
+		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM
+	},
+	{
+		.start		= IXP4XX_UART2_BASE_PHYS,
+		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM
+	}
+};
+
+static struct plat_serial8250_port compex42x_uart_data[] = {
+	{
+		.mapbase	= IXP4XX_UART1_BASE_PHYS,
+		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+		.irq		= IRQ_IXP4XX_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+	},
+	{
+		.mapbase	= IXP4XX_UART2_BASE_PHYS,
+		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+		.irq		= IRQ_IXP4XX_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+	},
+	{ },
+};
+
+static struct platform_device compex42x_uart = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev.platform_data	= compex42x_uart_data,
+	.num_resources		= 2,
+	.resource		= compex42x_uart_resources,
+};
+
+static struct eth_plat_info compex42x_plat_eth[] = {
+	{
+		.phy		= IXP4XX_ETH_PHY_MAX_ADDR,
+		.phy_mask	= 0xf0000,
+		.rxq		= 3,
+		.txreadyq	= 20,
+	}, {
+		.phy		= 3,
+		.rxq		= 4,
+		.txreadyq	= 21,
+	}
+};
+
+static struct platform_device compex42x_eth[] = {
+	{
+		.name			= "ixp4xx_eth",
+		.id			= IXP4XX_ETH_NPEB,
+		.dev.platform_data	= compex42x_plat_eth,
+		.dev.coherent_dma_mask	= DMA_BIT_MASK(32),
+	}, {
+		.name			= "ixp4xx_eth",
+		.id			= IXP4XX_ETH_NPEC,
+		.dev.platform_data	= compex42x_plat_eth + 1,
+		.dev.coherent_dma_mask	= DMA_BIT_MASK(32),
+	}
+};
+
+static struct platform_device *compex42x_devices[] __initdata = {
+	&compex42x_flash,
+	&compex42x_uart,
+	&compex42x_eth[0],
+	&compex42x_eth[1],
+};
+
+static void __init compex42x_init(void)
+{
+	ixp4xx_sys_init();
+
+	compex42x_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+	compex42x_flash_resource.end =
+		IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
+
+	platform_add_devices(compex42x_devices, ARRAY_SIZE(compex42x_devices));
+}
+
+MACHINE_START(COMPEXWP18, "Compex WP18 / NP18A")
+	/* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
+	.map_io		= ixp4xx_map_io,
+	.init_irq	= ixp4xx_init_irq,
+	.init_time	= ixp4xx_timer_init,
+	.atag_offset	= 0x0100,
+	.init_machine	= compex42x_init,
+#if defined(CONFIG_PCI)
+	.dma_zone_size	= SZ_64M,
+#endif
+	.restart	= ixp4xx_restart,
+MACHINE_END
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -69,7 +69,8 @@ struct hw_pci ixdp425_pci __initdata = {
 int __init ixdp425_pci_init(void)
 {
 	if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
-			machine_is_ixdp465() || machine_is_kixrp435())
+			machine_is_ixdp465() || machine_is_kixrp435() ||
+			machine_is_compex42x())
 		pci_common_init(&ixdp425_pci);
 	return 0;
 }
