// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2023 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/reset/mediatek,mt7988-resets.h>
#include <dt-bindings/thermal/thermal.h>

/* TOPRGU resets */
#define MT7988_TOPRGU_SGMII0_GRST		1
#define MT7988_TOPRGU_SGMII1_GRST		2
#define MT7988_TOPRGU_XFI0_GRST			12
#define MT7988_TOPRGU_XFI1_GRST			13
#define MT7988_TOPRGU_XFI_PEXTP0_GRST		14
#define MT7988_TOPRGU_XFI_PEXTP1_GRST		15
#define MT7988_TOPRGU_XFI_PLL_GRST		16

/ {
	compatible = "mediatek,mt7988a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cci: cci {
		compatible = "mediatek,mt7988-cci",
			     "mediatek,mt8183-cci";
		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
			 <&topckgen CLK_TOP_XTAL>;
		clock-names = "cci", "intermediate";
		operating-points-v2 = <&cci_opp>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a73";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			mediatek,cci = <&cci>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a73";
			reg = <0x1>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			mediatek,cci = <&cci>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a73";
			reg = <0x2>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			mediatek,cci = <&cci>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a73";
			reg = <0x3>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
				 <&topckgen CLK_TOP_XTAL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			mediatek,cci = <&cci>;
		};

		cluster0_opp: opp_table0 {
			compatible = "operating-points-v2";
			opp-shared;

			opp00 {
				opp-hz = /bits/ 64 <800000000>;
				opp-microvolt = <850000>;
			};

			opp01 {
				opp-hz = /bits/ 64 <1100000000>;
				opp-microvolt = <850000>;
			};

			opp02 {
				opp-hz = /bits/ 64 <1500000000>;
				opp-microvolt = <850000>;
			};

			opp03 {
				opp-hz = /bits/ 64 <1800000000>;
				opp-microvolt = <900000>;
			};
		};
	};

	cci_opp: opp_table_cci {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <480000000>;
			opp-microvolt = <850000>;
		};

		opp01 {
			opp-hz = /bits/ 64 <660000000>;
			opp-microvolt = <850000>;
		};

		opp02 {
			opp-hz = /bits/ 64 <900000000>;
			opp-microvolt = <850000>;
		};

		opp03 {
			opp-hz = /bits/ 64 <1080000000>;
			opp-microvolt = <900000>;
		};
	};

	clk40m: oscillator@0 {
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
		#clock-cells = <0>;
		clock-output-names = "clkxtal";
	};

	fan: pwm-fan {
		compatible = "pwm-fan";
		/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
		cooling-levels = <0 80 128 255>;
		#cooling-cells = <2>;
		#thermal-sensor-cells = <1>;
		status = "disabled";
	};

	pmu {
		compatible = "arm,cortex-a73-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reserved-memory {
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
		secmon_reserved: secmon@43000000 {
			reg = <0 0x43000000 0 0x50000>;
			no-map;
		};
	};

	soc {
		compatible = "simple-bus";
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
			      <0 0x0c080000 0 0x200000>, /* GICR */
			      <0 0x0c400000 0 0x2000>,   /* GICC */
			      <0 0x0c410000 0 0x1000>,   /* GICH */
			      <0 0x0c420000 0 0x2000>;   /* GICV */
			interrupt-parent = <&gic>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		phyfw: phy-firmware@f000000 {
			compatible = "mediatek,2p5gphy-fw";
			reg = <0 0x0f100000 0 0x20000>,
			      <0 0x0f0f0018 0 0x20>;
		};

		infracfg: infracfg@10001000 {
			compatible = "mediatek,mt7988-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		topckgen: topckgen@1001b000 {
			compatible = "mediatek,mt7988-topckgen", "syscon";
			reg = <0 0x1001b000 0 0x1000>;
			#clock-cells = <1>;
		};

		watchdog: watchdog@1001c000 {
			compatible = "mediatek,mt7988-wdt",
				     "mediatek,mt6589-wdt",
				     "syscon";
			reg = <0 0x1001c000 0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			#reset-cells = <1>;
		};

		apmixedsys: apmixedsys@1001e000 {
			compatible = "mediatek,mt7988-apmixedsys";
			reg = <0 0x1001e000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@1001f000 {
			compatible = "mediatek,mt7988-pinctrl", "syscon";
			reg = <0 0x1001f000 0 0x1000>,
			      <0 0x11c10000 0 0x1000>,
			      <0 0x11d00000 0 0x1000>,
			      <0 0x11d20000 0 0x1000>,
			      <0 0x11e00000 0 0x1000>,
			      <0 0x11f00000 0 0x1000>,
			      <0 0x1000b000 0 0x1000>;
			reg-names = "gpio_base", "iocfg_tr_base",
				    "iocfg_br_base", "iocfg_rb_base",
				    "iocfg_lb_base", "iocfg_tl_base", "eint";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 84>;
			interrupt-controller;
			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			#interrupt-cells = <2>;

			mdio0_pins: mdio0-pins {
				mux {
					function = "eth";
					groups = "mdc_mdio0";
				};

				conf {
					groups = "mdc_mdio0";
					drive-strength = <MTK_DRIVE_8mA>;
				};
			};

			i2c0_pins: i2c0-pins-g0 {
				mux {
					function = "i2c";
					groups = "i2c0_1";
				};
			};

			i2c1_pins: i2c1-pins-g0 {
				mux {
					function = "i2c";
					groups = "i2c1_0";
				};
			};

			i2c1_sfp_pins: i2c1-sfp-pins-g0 {
				mux {
					function = "i2c";
					groups = "i2c1_sfp";
				};
			};

			i2c2_pins: i2c2-pins {
				mux {
					function = "i2c";
					groups = "i2c2";
				};
			};

			i2c2_0_pins: i2c2-pins-g0 {
				mux {
					function = "i2c";
					groups = "i2c2_0";
				};
			};

			i2c2_1_pins: i2c2-pins-g1 {
				mux {
					function = "i2c";
					groups = "i2c2_1";
				};
			};

			gbe0_led0_pins: gbe0-led0-pins {
				mux {
					function = "led";
					groups = "gbe0_led0";
				};
			};

			gbe1_led0_pins: gbe1-led0-pins {
				mux {
					function = "led";
					groups = "gbe1_led0";
				};
			};

			gbe2_led0_pins: gbe2-led0-pins {
				mux {
					function = "led";
					groups = "gbe2_led0";
				};
			};

			gbe3_led0_pins: gbe3-led0-pins {
				mux {
					function = "led";
					groups = "gbe3_led0";
				};
			};

			gbe0_led1_pins: gbe0-led1-pins {
				mux {
					function = "led";
					groups = "gbe0_led1";
				};
			};

			gbe1_led1_pins: gbe1-led1-pins {
				mux {
					function = "led";
					groups = "gbe1_led1";
				};
			};

			gbe2_led1_pins: gbe2-led1-pins {
				mux {
					function = "led";
					groups = "gbe2_led1";
				};
			};

			gbe3_led1_pins: gbe3-led1-pins {
				mux {
					function = "led";
					groups = "gbe3_led1";
				};
			};

			i2p5gbe_led0_pins: 2p5gbe-led0-pins {
				mux {
					function = "led";
					groups = "2p5gbe_led0";
				};
			};

			i2p5gbe_led1_pins: 2p5gbe-led1-pins {
				mux {
					function = "led";
					groups = "2p5gbe_led1";
				};
			};

			mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
				mux {
					function = "flash";
					groups = "emmc_45";
				};
			};

			mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
				mux {
					function = "flash";
					groups = "emmc_51";
				};
			};

			mmc0_pins_sdcard: mmc0-pins-sdcard {
				mux {
					function = "flash";
					groups = "sdcard";
				};
			};

			uart0_pins: uart0-pins {
				mux {
					function = "uart";
					groups =  "uart0";
				};
			};

			uart1_0_pins: uart1-0-pins {
				mux {
					function = "uart";
					groups =  "uart1_0";
				};
			};

			uart1_1_pins: uart1-1-pins {
				mux {
					function = "uart";
					groups =  "uart1_1";
				};
			};

			uart1_2_pins: uart1-2-pins {
				mux {
					function = "uart";
					groups =  "uart1_2";
				};
			};

			uart1_2_lite_pins: uart1-2-lite-pins {
				mux {
					function = "uart";
					groups =  "uart1_2_lite";
				};
			};

			uart2_pins: uart2-pins {
				mux {
					function = "uart";
					groups =  "uart2";
				};
			};

			uart2_0_pins: uart2-0-pins {
				mux {
					function = "uart";
					groups =  "uart2_0";
				};
			};

			uart2_1_pins: uart2-1-pins {
				mux {
					function = "uart";
					groups =  "uart2_1";
				};
			};

			uart2_2_pins: uart2-2-pins {
				mux {
					function = "uart";
					groups =  "uart2_2";
				};
			};

			uart2_3_pins: uart2-3-pins {
				mux {
					function = "uart";
					groups =  "uart2_3";
				};
			};

			snfi_pins: snfi-pins {
				mux {
					function = "flash";
					groups = "snfi";
				};
			};

			spi0_pins: spi0-pins {
				mux {
					function = "spi";
					groups = "spi0";
				};
			};

			spi0_flash_pins: spi0-flash-pins {
				mux {
					function = "spi";
					groups = "spi0", "spi0_wp_hold";
				};
			};

			spi1_pins: spi1-pins {
				mux {
					function = "spi";
					groups = "spi1";
				};
			};

			spi2_pins: spi2-pins {
				mux {
					function = "spi";
					groups = "spi2";
				};
			};

			spi2_flash_pins: spi2-flash-pins {
				mux {
					function = "spi";
					groups = "spi2", "spi2_wp_hold";
				};
			};

			pcie0_pins: pcie0-pins {
				mux {
					function = "pcie";
					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
						 "pcie_wake_n0_0";
				};
			};

			pcie1_pins: pcie1-pins {
				mux {
					function = "pcie";
					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
						 "pcie_wake_n1_0";
				};
			};

			pcie2_pins: pcie2-pins {
				mux {
					function = "pcie";
					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
						 "pcie_wake_n2_0";
				};
			};

			pcie3_pins: pcie3-pins {
				mux {
					function = "pcie";
					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
						 "pcie_wake_n3_0";
				};
			};
		};

		pwm: pwm@10048000 {
			compatible = "mediatek,mt7988-pwm";
			reg = <0 0x10048000 0 0x1000>;
			#pwm-cells = <2>;
			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
				 <&infracfg CLK_INFRA_66M_PWM_CK1>,
				 <&infracfg CLK_INFRA_66M_PWM_CK2>,
				 <&infracfg CLK_INFRA_66M_PWM_CK3>,
				 <&infracfg CLK_INFRA_66M_PWM_CK4>,
				 <&infracfg CLK_INFRA_66M_PWM_CK5>,
				 <&infracfg CLK_INFRA_66M_PWM_CK6>,
				 <&infracfg CLK_INFRA_66M_PWM_CK7>,
				 <&infracfg CLK_INFRA_66M_PWM_CK8>;
			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
				      "pwm4","pwm5","pwm6","pwm7","pwm8";
			status = "disabled";
		};

		sgmiisys0: syscon@10060000 {
			compatible = "mediatek,mt7988-sgmiisys",
				     "mediatek,mt7988-sgmiisys0",
				     "syscon",
				     "simple-mfd";
			reg = <0 0x10060000 0 0x1000>;
			resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
			#clock-cells = <1>;

			sgmiipcs0: pcs {
				compatible = "mediatek,mt7988-sgmii";
				clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
					 <&sgmiisys0 CLK_SGM0_TX_EN>,
					 <&sgmiisys0 CLK_SGM0_RX_EN>;
				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
			};
		};

		sgmiisys1: syscon@10070000 {
			compatible = "mediatek,mt7988-sgmiisys",
				     "mediatek,mt7988-sgmiisys1",
				     "syscon",
				     "simple-mfd";
			reg = <0 0x10070000 0 0x1000>;
			resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
			#clock-cells = <1>;

			sgmiipcs1: pcs {
				compatible = "mediatek,mt7988-sgmii";
				clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
					 <&sgmiisys1 CLK_SGM1_TX_EN>,
					 <&sgmiisys1 CLK_SGM1_RX_EN>;
				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
			};
		};

		usxgmiisys0: pcs@10080000 {
			compatible = "mediatek,mt7988-usxgmiisys";
			reg = <0 0x10080000 0 0x1000>;
			resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
			clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
		};

		usxgmiisys1: pcs@10081000 {
			compatible = "mediatek,mt7988-usxgmiisys";
			reg = <0 0x10081000 0 0x1000>;
			resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
			clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
		};

		mcusys: mcusys@100e0000 {
			compatible = "mediatek,mt7988-mcusys", "syscon";
			reg = <0 0x100e0000 0 0x1000>;
			#clock-cells = <1>;
		};

		uart0: serial@11000000 {
			compatible = "mediatek,mt7986-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11000000 0 0x100>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
			/*
			 * 8250-mtk driver don't control "baud" clock since commit
			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
			 * still need to be passed to the driver to prevent probe fail
			 */
			clocks = <&topckgen CLK_TOP_UART_SEL>,
				 <&infracfg CLK_INFRA_52M_UART0_CK>;
			clock-names = "baud", "bus";
			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
					  <&infracfg CLK_INFRA_MUX_UART0_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
						 <&topckgen CLK_TOP_UART_SEL>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pins>;
			status = "disabled";
		};

		uart1: serial@11000100 {
			compatible = "mediatek,mt7986-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11000100 0 0x100>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
			/*
			 * 8250-mtk driver don't control "baud" clock since commit
			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
			 * still need to be passed to the driver to prevent probe fail
			 */
			clocks = <&topckgen CLK_TOP_UART_SEL>,
				 <&infracfg CLK_INFRA_52M_UART1_CK>;
			clock-names = "baud", "bus";
			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
					  <&infracfg CLK_INFRA_MUX_UART1_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
						 <&topckgen CLK_TOP_UART_SEL>;
			status = "disabled";
		};

		uart2: serial@11000200 {
			compatible = "mediatek,mt7986-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11000200 0 0x100>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			/*
			 * 8250-mtk driver don't control "baud" clock since commit
			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
			 * still need to be passed to the driver to prevent probe fail
			 */
			clocks = <&topckgen CLK_TOP_UART_SEL>,
				 <&infracfg CLK_INFRA_52M_UART2_CK>;
			clock-names = "baud", "bus";
			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
					  <&infracfg CLK_INFRA_MUX_UART2_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
						 <&topckgen CLK_TOP_UART_SEL>;
			status = "disabled";
		};

		snand: spi@11001000 {
			compatible = "mediatek,mt7986-snand";
			reg = <0 0x11001000 0 0x1000>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_SPINFI>,
				 <&infracfg CLK_INFRA_NFI>;
			clock-names = "pad_clk", "nfi_clk";
			assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
					  <&topckgen CLK_TOP_NFI1X_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
						 <&topckgen CLK_TOP_MPLL_D8>;
			nand-ecc-engine = <&bch>;
			mediatek,quad-spi;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&snfi_pins>;
			status = "disabled";
		};

		bch: ecc@11002000 {
			compatible = "mediatek,mt7686-ecc";
			reg = <0 0x11002000 0 0x1000>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
			clock-names = "nfiecc_clk";
			status = "disabled";
		};

		i2c0: i2c@11003000 {
			compatible = "mediatek,mt7988-i2c",
				     "mediatek,mt7981-i2c";
			reg = <0 0x11003000 0 0x1000>,
			      <0 0x10217080 0 0x80>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clock-div = <1>;
			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@11004000 {
			compatible = "mediatek,mt7988-i2c",
				     "mediatek,mt7981-i2c";
			reg = <0 0x11004000 0 0x1000>,
			      <0 0x10217100 0 0x80>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clock-div = <1>;
			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@11005000 {
			compatible = "mediatek,mt7988-i2c",
				"mediatek,mt7981-i2c";
			reg = <0 0x11005000 0 0x1000>,
			      <0 0x10217180 0 0x80>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			clock-div = <1>;
			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@11007000 {
			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
			reg = <0 0x11007000 0 0x100>;
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_MPLL_D2>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_104M_SPI0>,
				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
			clock-names = "parent-clk", "sel-clk", "spi-clk",
				      "spi-hclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@11008000 {
			compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
			reg = <0 0x11008000 0 0x100>;
			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_MPLL_D2>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_104M_SPI1>,
				 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
			clock-names = "parent-clk", "sel-clk", "spi-clk",
				      "spi-hclk";
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi1_pins>;
			status = "disabled";
		};

		spi2: spi@11009000 {
			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
			reg = <0 0x11009000 0 0x100>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_MPLL_D2>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
				 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
			clock-names = "parent-clk", "sel-clk", "spi-clk",
				      "spi-hclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		lvts: lvts@1100a000 {
			compatible = "mediatek,mt7988-lvts-ap";
			reg = <0 0x1100a000 0 0x1000>;
			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
			clock-names = "lvts_clk";
			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
			nvmem-cells = <&lvts_calibration>;
			nvmem-cell-names = "lvts-calib-data-1";
			#thermal-sensor-cells = <1>;
		};

		ssusb0: usb@11190000 {
			compatible = "mediatek,mt7988-xhci",
				     "mediatek,mtk-xhci";
			reg = <0 0x11190000 0 0x2e00>,
			      <0 0x11193e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&xphyu2port0 PHY_TYPE_USB2>,
			       <&xphyu3port0 PHY_TYPE_USB3>;
			clocks = <&infracfg CLK_INFRA_USB_SYS>,
				 <&infracfg CLK_INFRA_USB_XHCI>,
				 <&infracfg CLK_INFRA_USB_REF>,
				 <&infracfg CLK_INFRA_66M_USB_HCK>,
				 <&infracfg CLK_INFRA_133M_USB_HCK>;
			clock-names = "sys_ck",
				      "xhci_ck",
				      "ref_ck",
				      "mcu_ck",
				      "dma_ck";
			#address-cells = <2>;
			#size-cells = <2>;
			mediatek,p0_speed_fixup;
			status = "disabled";
		};

		ssusb1: usb@11200000 {
			compatible = "mediatek,mt7988-xhci",
				     "mediatek,mtk-xhci";
			reg = <0 0x11200000 0 0x2e00>,
			      <0 0x11203e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&tphyu2port0 PHY_TYPE_USB2>,
			       <&tphyu3port0 PHY_TYPE_USB3>;
			clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
				 <&infracfg CLK_INFRA_USB_CK_P1>,
				 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
			clock-names = "sys_ck",
				      "xhci_ck",
				      "ref_ck",
				      "mcu_ck",
				      "dma_ck";
			#address-cells = <2>;
			#size-cells = <2>;
			status = "disabled";
		};

		afe: audio-controller@11210000 {
			compatible = "mediatek,mt79xx-audio";
			reg = <0 0x11210000 0 0x9000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
				 <&infracfg CLK_INFRA_AUD_26M>,
				 <&infracfg CLK_INFRA_AUD_L>,
				 <&infracfg CLK_INFRA_AUD_AUD>,
				 <&infracfg CLK_INFRA_AUD_EG2>,
				 <&topckgen CLK_TOP_AUD_SEL>,
				 <&topckgen CLK_TOP_AUD_I2S_M>;
			clock-names = "aud_bus_ck",
				      "aud_26m_ck",
				      "aud_l_ck",
				      "aud_aud_ck",
				      "aud_eg2_ck",
				      "aud_sel",
				      "aud_i2s_m";
			assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
					  <&topckgen CLK_TOP_A1SYS_SEL>,
					  <&topckgen CLK_TOP_AUD_L_SEL>,
					  <&topckgen CLK_TOP_A_TUNER_SEL>;
			assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
						 <&topckgen CLK_TOP_APLL2_D4>,
						 <&apmixedsys CLK_APMIXED_APLL2>,
						 <&topckgen CLK_TOP_APLL2_D4>;
			status = "disabled";
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt7986-mmc",
				     "mediatek,mt7981-mmc";
			reg = <0 0x11230000 0 0x1000>,
			      <0 0x11D60000 0 0x1000>;
			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_MSDC400>,
				 <&infracfg CLK_INFRA_MSDC2_HCK>,
				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
			clock-names = "source",
				      "hclk",
				      "axi_cg",
				      "ahb_cg";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		pcie2: pcie@11280000 {
			compatible = "mediatek,mt7988-pcie",
				     "mediatek,mt7986-pcie",
				     "mediatek,mt8192-pcie";
			reg = <0 0x11280000 0 0x2000>;
			reg-names = "pcie-mac";
			ranges = <0x81000000 0x00 0x20000000 0x00
				  0x20000000 0x00 0x00200000>,
				 <0x82000000 0x00 0x20200000 0x00
				  0x20200000 0x00 0x07e00000>;
			device_type = "pci";
			linux,pci-domain = <3>;
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			bus-range = <0x00 0xff>;
			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
				 <&topckgen CLK_TOP_PEXTP_P2_SEL>;
			clock-names = "pl_250m", "tl_26m", "peri_26m",
				      "top_133m", "pextp_clk";
			pinctrl-names = "default";
			pinctrl-0 = <&pcie2_pins>;
			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
			phy-names = "pcie-phy";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
					<0 0 0 2 &pcie_intc2 1>,
					<0 0 0 3 &pcie_intc2 2>,
					<0 0 0 4 &pcie_intc2 3>;
			#address-cells = <3>;
			#size-cells = <2>;
			status = "disabled";

			pcie_intc2: interrupt-controller {
				#address-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		pcie3: pcie@11290000 {
			compatible = "mediatek,mt7988-pcie",
				     "mediatek,mt7986-pcie",
				     "mediatek,mt8192-pcie";
			reg = <0 0x11290000 0 0x2000>;
			reg-names = "pcie-mac";
			ranges = <0x81000000 0x00 0x28000000 0x00
				  0x28000000 0x00 0x00200000>,
				 <0x82000000 0x00 0x28200000 0x00
				  0x28200000 0x00 0x07e00000>;
			device_type = "pci";
			linux,pci-domain = <2>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			bus-range = <0x00 0xff>;
			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
				 <&topckgen CLK_TOP_PEXTP_P3_SEL>;
			clock-names = "pl_250m", "tl_26m", "peri_26m",
				      "top_133m", "pextp_clk";
			pinctrl-names = "default";
			pinctrl-0 = <&pcie3_pins>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
					<0 0 0 2 &pcie_intc3 1>,
					<0 0 0 3 &pcie_intc3 2>,
					<0 0 0 4 &pcie_intc3 3>;
			#address-cells = <3>;
			#size-cells = <2>;
			status = "disabled";

			pcie_intc3: interrupt-controller {
				#address-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		pcie0: pcie@11300000 {
			compatible = "mediatek,mt7988-pcie",
				     "mediatek,mt7986-pcie",
				     "mediatek,mt8192-pcie";
			reg = <0 0x11300000 0 0x2000>;
			reg-names = "pcie-mac";
			ranges = <0x81000000 0x00 0x30000000 0x00
				  0x30000000 0x00 0x00200000>,
				 <0x82000000 0x00 0x30200000 0x00
				  0x30200000 0x00 0x07e00000>;
			device_type = "pci";
			linux,pci-domain = <0>;
			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
			bus-range = <0x00 0xff>;
			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
				 <&topckgen CLK_TOP_PEXTP_P0_SEL>;
			clock-names = "pl_250m", "tl_26m", "peri_26m",
				      "top_133m", "pextp_clk";
			pinctrl-names = "default";
			pinctrl-0 = <&pcie0_pins>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
					<0 0 0 2 &pcie_intc0 1>,
					<0 0 0 3 &pcie_intc0 2>,
					<0 0 0 4 &pcie_intc0 3>;
			#address-cells = <3>;
			#size-cells = <2>;
			status = "disabled";

			pcie_intc0: interrupt-controller {
				#address-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		pcie1: pcie@11310000 {
			compatible = "mediatek,mt7988-pcie",
				     "mediatek,mt7986-pcie",
				     "mediatek,mt8192-pcie";
			reg = <0 0x11310000 0 0x2000>;
			reg-names = "pcie-mac";
			ranges = <0x81000000 0x00 0x38000000 0x00
				  0x38000000 0x00 0x00200000>,
				 <0x82000000 0x00 0x38200000 0x00
				  0x38200000 0x00 0x07e00000>;
			device_type = "pci";
			linux,pci-domain = <1>;
			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			bus-range = <0x00 0xff>;
			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
				 <&topckgen CLK_TOP_PEXTP_P1_SEL>;
			clock-names = "pl_250m", "tl_26m", "peri_26m",
				      "top_133m", "pextp_clk";
			pinctrl-names = "default";
			pinctrl-0 = <&pcie1_pins>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
					<0 0 0 2 &pcie_intc1 1>,
					<0 0 0 3 &pcie_intc1 2>,
					<0 0 0 4 &pcie_intc1 3>;
			#address-cells = <3>;
			#size-cells = <2>;
			status = "disabled";

			pcie_intc1: interrupt-controller {
				#address-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		tphy: tphy@11c50000 {
			compatible = "mediatek,mt7988",
				     "mediatek,generic-tphy-v2";
			ranges;
			#address-cells = <2>;
			#size-cells = <2>;
			status = "disabled";

			tphyu2port0: usb-phy@11c50000 {
				reg = <0 0x11c50000 0 0x700>;
				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
				clock-names = "ref";
				#phy-cells = <1>;
			};

			tphyu3port0: usb-phy@11c50700 {
				reg = <0 0x11c50700 0 0x900>;
				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
				clock-names = "ref";
				#phy-cells = <1>;
				mediatek,usb3-pll-ssc-delta;
				mediatek,usb3-pll-ssc-delta1;
			};
		};

		topmisc: topmisc@11d10000 {
			compatible = "mediatek,mt7988-topmisc", "syscon",
				     "mediatek,mt7988-power-controller";
			reg = <0 0x11d10000 0 0x10000>;
			#clock-cells = <1>;
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		xphy: xphy@11e10000 {
			compatible = "mediatek,mt7988",
				     "mediatek,xsphy";
			ranges;
			#address-cells = <2>;
			#size-cells = <2>;
			status = "disabled";

			xphyu2port0: usb-phy@11e10000 {
				reg = <0 0x11e10000 0 0x400>;
				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
				clock-names = "ref";
				#phy-cells = <1>;
			};

			xphyu3port0: usb-phy@11e13000 {
				reg = <0 0x11e13400 0 0x500>;
				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
				clock-names = "ref";
				#phy-cells = <1>;
				mediatek,syscon-type = <&topmisc 0x218 0>;
			};
		};

		xfi_tphy0: phy@11f20000 {
			compatible = "mediatek,mt7988-xfi-tphy";
			reg = <0 0x11f20000 0 0x10000>;
			resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
			clock-names = "xfipll", "topxtal";
			mediatek,usxgmii-performance-errata;
			#phy-cells = <0>;
		};

		xfi_tphy1: phy@11f30000 {
			compatible = "mediatek,mt7988-xfi-tphy";
			reg = <0 0x11f30000 0 0x10000>;
			resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
			clock-names = "xfipll", "topxtal";
			#phy-cells = <0>;
		};

		xfi_pll: clock-controller@11f40000 {
			compatible = "mediatek,mt7988-xfi-pll";
			reg = <0 0x11f40000 0 0x1000>;
			resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
			#clock-cells = <1>;
		};

		efuse: efuse@11f50000 {
			compatible = "mediatek,efuse";
			reg = <0 0x11f50000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			lvts_calibration: calib@918 {
				reg = <0x918 0x28>;
			};

			phy_calibration_p0: calib@940 {
				reg = <0x940 0x10>;
			};

			phy_calibration_p1: calib@954 {
				reg = <0x954 0x10>;
			};

			phy_calibration_p2: calib@968 {
				reg = <0x968 0x10>;
			};

			phy_calibration_p3: calib@97c {
				reg = <0x97c 0x10>;
			};

			cpufreq_calibration: calib@278 {
				reg = <0x278 0x1>;
			};
		};

		ethsys: syscon@15000000 {
			compatible = "mediatek,mt7988-ethsys", "syscon";
			reg = <0 0x15000000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
		};

		switch: switch@15020000 {
			compatible = "mediatek,mt7988-switch";
			reg = <0 0x15020000 0 0x8000>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
			#address-cells = <1>;
			#size-cells = <1>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				gsw_port0: port@0 {
					reg = <0>;
					label = "lan0";
					phy-mode = "internal";
					phy-handle = <&gsw_phy0>;
				};

				gsw_port1: port@1 {
					reg = <1>;
					label = "lan1";
					phy-mode = "internal";
					phy-handle = <&gsw_phy1>;
				};

				gsw_port2: port@2 {
					reg = <2>;
					label = "lan2";
					phy-mode = "internal";
					phy-handle = <&gsw_phy2>;
				};

				gsw_port3: port@3 {
					reg = <3>;
					label = "lan3";
					phy-mode = "internal";
					phy-handle = <&gsw_phy3>;
				};

				port@6 {
					reg = <6>;
					ethernet = <&gmac0>;
					phy-mode = "internal";

					fixed-link {
						speed = <10000>;
						full-duplex;
						pause;
					};
				};
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				mediatek,pio = <&pio>;

				gsw_phy0: ethernet-phy@0 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <0>;
					interrupts = <0>;
					phy-mode = "internal";
					nvmem-cells = <&phy_calibration_p0>;
					nvmem-cell-names = "phy-cal-data";

					leds {
						#address-cells = <1>;
						#size-cells = <0>;

						gsw_phy0_led0: gsw-phy0-led0@0 {
							reg = <0>;
							function = LED_FUNCTION_LAN;
							status = "disabled";
						};

						gsw_phy0_led1: gsw-phy0-led1@1 {
							reg = <1>;
							function = LED_FUNCTION_LAN;
							status = "disabled";
						};
					};
				};

				gsw_phy1: ethernet-phy@1 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <1>;
					interrupts = <1>;
					phy-mode = "internal";
					nvmem-cells = <&phy_calibration_p1>;
					nvmem-cell-names = "phy-cal-data";

					leds {
						#address-cells = <1>;
						#size-cells = <0>;

						gsw_phy1_led0: gsw-phy1-led0@0 {
							reg = <0>;
							function = LED_FUNCTION_LAN;
							status = "disabled";
						};

						gsw_phy1_led1: gsw-phy1-led1@1 {
							reg = <1>;
							function = LED_FUNCTION_LAN;
							status = "disabled";
						};
					};
				};

				gsw_phy2: ethernet-phy@2 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <2>;
					interrupts = <2>;
					phy-mode = "internal";
					nvmem-cells = <&phy_calibration_p2>;
					nvmem-cell-names = "phy-cal-data";

					leds {
						#address-cells = <1>;
						#size-cells = <0>;

						gsw_phy2_led0: gsw-phy2-led0@0 {
							reg = <0>;
							function = LED_FUNCTION_LAN;
							status = "disabled";
						};

						gsw_phy2_led1: gsw-phy2-led1@1 {
							reg = <1>;
							function = LED_FUNCTION_LAN;
							status = "disabled";
						};
					};
				};

				gsw_phy3: ethernet-phy@3 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <3>;
					interrupts = <3>;
					phy-mode = "internal";
					nvmem-cells = <&phy_calibration_p3>;
					nvmem-cell-names = "phy-cal-data";

					leds {
						#address-cells = <1>;
						#size-cells = <0>;

						gsw_phy3_led0: gsw-phy3-led0@0 {
							reg = <0>;
							function = LED_FUNCTION_LAN;
							status = "disabled";
						};

						gsw_phy3_led1: gsw-phy3-led1@1 {
							reg = <1>;
							function = LED_FUNCTION_LAN;
							status = "disabled";
						};
					};
				};
			};
		};

		ethwarp: clock-controller@15031000 {
			compatible = "mediatek,mt7988-ethwarp";
			reg = <0 0x15031000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		eth: ethernet@15100000 {
			compatible = "mediatek,mt7988-eth";
			reg = <0 0x15100000 0 0x80000>,
			      <0 0x15400000 0 0x380000>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
				 <&ethsys CLK_ETHDMA_XGP2_EN>,
				 <&ethsys CLK_ETHDMA_XGP3_EN>,
				 <&ethsys CLK_ETHDMA_FE_EN>,
				 <&ethsys CLK_ETHDMA_GP2_EN>,
				 <&ethsys CLK_ETHDMA_GP1_EN>,
				 <&ethsys CLK_ETHDMA_GP3_EN>,
				 <&ethsys CLK_ETHDMA_ESW_EN>,
				 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
				 <&topckgen CLK_TOP_ETH_SYS_SEL>,
				 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
				 <&topckgen CLK_TOP_ETH_MII_SEL>,
				 <&topckgen CLK_TOP_NETSYS_SEL>,
				 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
				 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
				 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
			clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
				      "gp3", "esw", "crypto",
				      "ethwarp_wocpu2", "ethwarp_wocpu1",
				      "ethwarp_wocpu0", "top_eth_gmii_sel",
				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
				      "top_eth_sys_sel", "top_eth_xgmii_sel",
				      "top_eth_mii_sel", "top_netsys_sel",
				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
				      "top_netsys_sync_250m_sel",
				      "top_netsys_ppefb_250m_sel",
				      "top_netsys_warp_sel";
			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
					  <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
					  <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
					  <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
					  <&topckgen CLK_TOP_SGM_0_SEL>,
					  <&topckgen CLK_TOP_SGM_1_SEL>;
			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
						 <&topckgen CLK_TOP_NET1PLL_D4>,
						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
						 <&apmixedsys CLK_APMIXED_SGMPLL>,
						 <&apmixedsys CLK_APMIXED_SGMPLL>;
			mediatek,ethsys = <&ethsys>;
			mediatek,infracfg = <&topmisc>;
			#address-cells = <1>;
			#size-cells = <0>;

			gmac0: mac@0 {
				compatible = "mediatek,eth-mac";
				reg = <0>;
				phy-mode = "internal";
				status = "disabled";

				fixed-link {
					speed = <10000>;
					full-duplex;
					pause;
				};
			};

			gmac1: mac@1 {
				compatible = "mediatek,eth-mac";
				reg = <1>;
				status = "disabled";
				pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
				phys = <&xfi_tphy1>;
			};

			gmac2: mac@2 {
				compatible = "mediatek,eth-mac";
				reg = <2>;
				status = "disabled";
				pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
				phys = <&xfi_tphy0>;
			};

			mdio_bus: mdio-bus {
				#address-cells = <1>;
				#size-cells = <0>;

				/* internal 2.5G PHY */
				int_2p5g_phy: ethernet-phy@15 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <15>;
					phy-mode = "internal";
				};
			};
		};

		crypto: crypto@15600000 {
			compatible = "inside-secure,safexcel-eip197b";
			reg = <0 0x15600000 0 0x180000>;
			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ring0", "ring1", "ring2", "ring3";
			status = "okay";
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;
			thermal-sensors = <&lvts 0>;

			trips {
				cpu_trip_crit: crit {
					temperature = <125000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu_trip_hot: hot {
					temperature = <120000>;
					hysteresis = <2000>;
					type = "hot";
				};

				cpu_trip_active_high: active-high {
					temperature = <115000>;
					hysteresis = <2000>;
					type = "active";
				};

				cpu_trip_active_med: active-med {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "active";
				};

				cpu_trip_active_low: active-low {
					temperature = <40000>;
					hysteresis = <2000>;
					type = "active";
				};
			};

			cooling-maps {
				cpu-active-high {
				/* active: set fan to cooling level 2 */
					cooling-device = <&fan 3 3>;
					trip = <&cpu_trip_active_high>;
				};

				cpu-active-low {
				/* active: set fan to cooling level 1 */
					cooling-device = <&fan 2 2>;
					trip = <&cpu_trip_active_med>;
				};

				cpu-passive {
				/* passive: set fan to cooling level 0 */
					cooling-device = <&fan 1 1>;
					trip = <&cpu_trip_active_low>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};
};
